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semiconductor group 1 1998-10-01 ? 2 097 152 words by 8-bit organization ? 0 to 70 c operating temperature ? hyper page mode-edo-operation ? performance: ? power dissipation: ? read, write, read-modify-write, cas-before- ras refresh, ras-only refresh, hidden refresh and test mode ? all inputs, outputs and clocks fully ttl (5 v versions) and lv-ttl (3.3 v version)-compatible ? 2048 refresh cycles / 32 ms (2k-refresh) ? plastic package: p-soj-28-3 400 mil -50 -60 t rac ras access time 50 60 ns t cac cas access time 13 15 ns t aa access time from address 25 30 ns t rc read/write cycle time 84 104 ns t hpc hyper page mode (edo) cycle time 20 25 ns hyb 5117805 hyb 3117805 -50 -60 -50 -60 power supply 5 10% 3.3 0.3 v active 440 385 288 252 mw ttl standby 11 7.2 mw cmos standby 5.5 3.6 mw 2m 8-bit dynamic ram 2k refresh (hyper page mode-edo) advanced information hyb 5117805/bsj-50/-60 hyb 3117805/bsj-50/-60
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 2 1998-10-01 the hyb 5(3)117805 are 16 mbit dynamic rams based on the die revisions g & f and organized as 2 097 152 words by 8-bits. the hyb 5(3)117805 utilizes a submicron cmos silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 5(3)117805bj to be packaged in a standard soj-28 plastic packages. package with 400 mil width are available. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. ordering information type ordering code package descriptions hyb 5117805bsj-50 q67100-q1104 p-soj-28-3 400 mil 5 v 50 ns edo-dram hyb 5117805bsj-60 q67100-q1105 p-soj-28-3 400 mil 5 v 60 ns edo-dram hyb 3117805bsj-50 on request p-soj-28-3 400 mil 3.3 v 50 ns edo-dram hyb 3117805bsj-60 on request p-soj-28-3 400 mil 3.3 v 60 ns edo-dram pin names and configuration a0 - a10 row address inputs a0 - a9 column address inputs ras row address strobe oe output enable i/o1 - i/o8 data input/output cas column address strobe we read/write input v cc power supply + 5 v for hyb 5117800 + 3.3 v for hyb 3117805 v ss ground (0 v) n.c. not connected 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a5 oe i/o5 cas a0 a1 a2 i/o3 i/o4 we ras n.c. a10 ss v cc v a9 i/o8 i/o7 ss v i/o1 i/o2 v cc a3 a6 a7 28 27 26 a8 i/o6 spp02803 a4 p-soj-28 400 mil
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 3 1998-10-01 block diagram spb03456 & no.2 clock generator address column buffers (10) controller refresh refresh counter (11) buffers (11) row address generator no.1 clock 11 10 a0 a1 a2 a3 a4 a5 a6 a7 a8 11 row decoder ras 2048 x 1024 x 8 memory array 2048 1024 x 8 sense amplifier i/o gating 10 column decoder buffer data in data out buffer i/o1 8 8 oe voltage down v cc v cc 11 4 a9 (internal) generator cas we a10 i/o2 i/o8
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 4 1998-10-01 absolute maximum ratings operating temperature range ........................................................................................... 0 to 70 c storage temperature range....................................................................................... C 55 to 150 c input/output voltage (5 v versions) .................................................... C 0.5 to min ( v cc + 0.5, 7.0) v input/output voltage (3.3 v versions) ................................................. C 0.5 to min ( v cc + 0.5, 4.6) v power supply voltage (5 v versions) ....................................................................... C 1.0 v to 7.0 v power supply voltage (3.3 v versions) .................................................................... C 1.0 v to 4.6 v power dissipation (5 v versions) ............................................................................................. 1. 0 w power dissipation (3.3 v versions) .......................................................................................... 0.5 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect dev ice reliability. dc characteristics t a = 0 to 70 c, v ss = 0 v, t t = 2 ns parameter symbol limit values unit test condition min. max. 5 v versions power supply voltage v cc 4.5 5.5 v input high voltage v ih 2.4 v cc + 0.5 v 1 input low voltage v il C 0.5 0.8 v 1 output high voltage ( i out = C 5 ma) v oh 2.4 C v 1 output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1 3.3 v versions power supply voltage v cc 3.0 3.6 v input high voltage v ih 2.0 v cc + 0.5 v 1 input low voltage v il C 0.5 0.8 v 1 ttl output high voltage ( i out = C 2 ma) v oh 2.4 C v 1 ttl output low voltage ( i out = 2 ma) v ol C 0.4 v 1 cmos output high voltage ( i out = C 100 m a) v oh v cc C 0.2 C v cmos output low voltage ( i out = 100 m a) v ol C 0.2 v common parameters input leakage current (0 v v ih v cc + 0.3 v, all other pins = 0 v) i i(l) C 10 10 m a 1 output leakage current (do is disabled, 0 v v out v cc + 0.3 v) i o(l) C 10 10 m a 1
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 5 1998-10-01 average v cc supply current -50 ns version -60 ns version ( ras, cas, address cycling: t rc = t rc min. ) i cc1 C C 80 70 ma ma 2, 3, )4 2, 3, 4 standby v cc supply current ( ras = cas = v ih ) i cc2 C2maC average v cc supply current, during ras-only refresh cycles -50 ns version -60 ns version ( ras cycling, cas = v ih , t rc = t rc min. ) i cc3 C C 80 70 ma ma 2, 4 2, 4 average v cc supply current, during hyper page mode (edo) -50 ns version -60 ns version ( ras = v il , cas, address cycling: t pc = t pc min. ) i cc4 C C 35 30 ma ma 2, 3, 4 2, 3, 4 standby v cc supply current ( ras = cas = v cc C 0.2 v) i cc5 C1ma 1 average v cc supply current, during cas- before- ras refresh mode -50 ns version -60 ns version ( ras, cas cycling: t rc = t rc min. ) i cc6 C C 80 70 ma ma 2, 4 2, 4 capacitance t a = 0 to 70 c, v cc = 5 v 10 %, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a10) c i1 C5pf input capacitance ( ras, cas, we, oe) c i2 C7pf i/o capacitance (i/o1 - i/o8) c io C7pf dc characteristics (contd) t a = 0 to 70 c, v ss = 0 v, t t = 2 ns parameter symbol limit values unit test condition min. max.
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 6 1998-10-01 ac characteristics 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max. common parameters random read or write cycle time t rc 84 C 104 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 10k 60 10k ns cas pulse width t cas 8 10k 10 10k ns row address setup time t asr 0C0Cns row address hold time t rah 8 C 10 C ns column address setup time t asc 0C0Cns column address hold time t cah 8 C 10 C ns ras to cas delay time t rcd 12 37 14 45 ns ras to column address delay t rad 10 25 12 30 ns ras hold time t rsh 13 C 15 C ns cas hold time t csh 40 C 50 C ns cas to ras precharge time t crp 5C5Cns transition time (rise and fall) t t 1 50 1 50 ns 7 refresh period t ref C 32 C 32 ms read cycle access time from ras t rac C 50 C 60 ns 8, 9 access time from cas t cac C 13 C 15 ns 8, 9 access time from column address t aa C 25 C 30 ns 8, 10 oe access time t oea C 13 C 15 ns column address to ras lead time t ral 25 C 30 C ns read command setup time t rcs 0C0Cns read command hold time t rch 0C0Cns 11 read command hold time referenced to ras t rrh 0C0Cns 11 cas to output in low-z t clz 0C0Cns 8 output buffer turn-off delay t off 0 13 0 15 ns 12 output turn-off delay from oe t oez 0 13 0 15 ns 12
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 7 1998-10-01 data to cas low delay t dzc 0C0Cns 13 data to oe low delay t dzo 0C0Cns 13 cas high to data delay t cdd 10 C 13 C ns 14 oe high to data delay t odd 10 C 13 C ns 14 write cycle write command hold time t wch 8 C 10 C ns write command pulse width t wp 8 C 10 C ns write command setup time t wcs 0C0Cns 15 write command to ras lead time t rwl 8 C 10 C ns write command to cas lead time t cwl 8 C 10 C ns data setup time t ds 0C0Cns 16 data hold time t dh 8 C 10 C ns 16 read-modify-write cycle read-write cycle time t rwc 113 C 138 C ns ras to we delay time t rwd 64 C 77 C ns 15 cas to we delay time t cwd 27 C 32 C ns 15 column address to we delay time t awd 39 C 47 C ns 15 oe command hold time t oeh 10 C 13 C ns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 20 C 25 C ns cas precharge time t cp 8 C 10 C ns access time from cas precharge t cpa C 27 C 32 ns 7 output data hold time t coh 5C5Cns ras pulse width in edo mode t ras 50 200k 60 200k ns cas precharge to ras delay t rhcp 27 C 32 C ns oe setup time prior to cas t oes 5C5C5 ac characteristics (contd) 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 8 1998-10-01 hyper page mode (edo) read-modify-write cycle hyper page mode (edo) read-write cycle time t prwc 58 C 68 C ns cas precharge to we t cpwd 41 C 49 C ns cas-before- ras refresh cycle cas setup time t csr 10 C 10 C ns cas hold time t chr 10 C 10 C ns ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C ns cas-before- ras counter test cycle cas precharge time ( cas-before- ras counter test cycle) t cpt 35 C 40 C ns test mode write command setup time t wts 10 C 10 C ns write command hold time t wth 10 C 10 C ns cas hold time t chrt 30 C 30 C ns ras hold time in test mode t raht 30 C 30 C ns ac characteristics (contd) 5, 6 t a = 0 to 70 c, v cc = 5 v 10 % / v cc = 3.3 v 0.3 v, t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 9 1998-10-01 notes 1. all voltages are referenced to v ss . 2. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3. i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4. address can be changed once or less while ras = v il . in case of i cc4 it can be changed once or less during a hyper page mode (edo) cycle 5. an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6. ac measurements assume t t = 2 ns. 7. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8. measured with the specified current load and 100 pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t aa , t cpa , t oea . t cac is measured from tristate. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10.operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11.either t rch or t rrh must be satisfied for a read cycle. 12. t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas, whichever occurs last. 13.either t dzc or t dzo must be satisfied. 14.either t cdd or t odd must be satisfied. 15. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16.these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles.
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 10 1998-10-01 read cycle spt03025 "h" or "l" oea cac ral t oh ol v (inputs) (outputs) i/o i/o v ih v il v oe we v il v ih v il v ih rac t hi dzo z t clz t t dzc t rcs aa t t v address v il v ih il cas ras il v ih v v ih t rad asr t row t column rah asc t cah t t rcd t csh t t ras t t odd rrh valid data out oez t t cdd off t hi z t t rsh cas t rc t rch asr t row crp t t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 11 1998-10-01 write cycle (early write) spt03026 "h" or "l" rwl ral wcs oh (inputs) (outputs) i/o i/o il v ol v v v ih oe we ih v il v v il v ih t valid ds t dh data in wch t t wp t v address ih v v il il cas ras v ih ih v v il t rad asr t t rah row t column asc t cwl t cah t t rcd t csh t t ras t z hi t rc cas rsh t asr t row crp t t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 12 1998-10-01 write cycle ( oe controlled write) spt03027 "h" or "l" ds ral cas v oh v (inputs) (outputs) i/o i/o v v ol il v ih oe we v il il v ih v ih t dzo hi z t clz t oea t oez t dzc odd t t v address il v v ih cas ras v il v ih il v ih rad asr t rah t row t t column asc t cah rcd t t t csh t ras t hi valid data t dh oeh t z rwl cwl t t wp t rsh t asr t row crp t t rc t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 13 1998-10-01 read-write (read-modify-write) cycle spt03028 "h" or "l" awd oea csh rwd oh i/o (outputs) v ol (inputs) i/o il v v v ih oe we v il v ih v il v ih rac t t dzc t dzo t clz t cac t rcs t aa t v address v il v ih cas ras ih v il v v il ih rah row asr t t rad t column asc t t t cah t rcd t t t wp data out ds odd oez t t t t data in valid t dh oeh row t cwd t cas t t rsh rwl t t cwl asr t crp t rp t rwc t ras
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 14 1998-10-01 hyper page mode (edo) read cycle spt03038 "h" or "l" data column t t oh ol il ih il ih i/o (output) v v v oe we v v v rcs cac t clz rac t aa t t oes oea t t ih il il ih ih il address v v cas ras v v v v rcd asc column row asr t rad t t rah t t crp t 1 csh cah t asc t hpc cas t t t cp t rch t out out t coh out 1 data aa t cpa t cac t t coh 2 data t aa cpa t cac t t n oez off crp rp rhcp column 2 cah t cas t n t cah asc t t ral rrh t rsh t cas t t t ras t t
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 15 1998-10-01 hyper page mode (edo) early write cycle spt03039 "h" or "l" ds data column t ih v i/o (input) oe v v il ih v il we v v il ih data t ds wcs t in 1 t dh t wp cwl t t wch t t wcs cas address v il v ih il v ras v ih il v v ih t t asc column address row asr t rad t rah t t crp t rcd 1 t csh cah asc t hpc cas t t cp t data ds in 2 t dh t cwl wch wp t t t t wcs in n t dh t t wch wp t cwl crp rp t column 2 cah t asc t t cas rwl t n t cah t ral rsh t cas t rhcp t t ras
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 16 1998-10-01 hyper page mode (edo) late write and read-modify-write cycle spt03031 "h" or "l" il data rac (outputs) i/o v oh ol v out data oez t i/o (inputs) oe clz t v il v ih dzc t t cac t ds dzo t odd t v il ih v t awd t aa t oea t t oeh aa ds aa out data t out data oez oez t odd in dh t t cpa t dzc t t in data dh t t t cac t dzc t t cpa oeh clz t wp t t oea t awd t clz t wp t oea t awd t in data ds t dh t odd t wp t oeh t address we cas v rcs v v ih t row v il ih t cwd t cwl rwd t column il v asr t t rah asc t rad t ih v rcd t t cah cas t ras il v v ih t csh cwd cwl t cwd t column cpwd t t t cpwd column prwc asc t cah t t cp cas t t asc t t cah cwl t rwl t row crp t ral rsh cas t t t asr t ras t t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 17 1998-10-01 ras-only refresh cycle spt03032 "h" or "l" oh ol (outputs) address i/o v v v il ih v row cas ras il v v ih v il ih v rah asr t t ras t row z hi t rc t rpc asr t crp t rp t
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 18 1998-10-01 cas-before- ras refresh cycle spt03033 "h" or "l" v il ih ih il ol oh il (outputs) i/o v v (inputs) oe i/o v v v v t off oez t t cdd odd t ih il ih ih il we cas v v v ras v v wrp csr t t cp t rpc t rp t t wrh t chr hi z ras t rc t t rpc t rp t crp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 19 1998-10-01 hidden refresh cycle (read) cycle v clz i/o (outputs) ol v "h" or "l" oh v i/o (inputs) il v ih v t rac t dzo t oe v il ih v we il ih v dzc t valid data out spt03034 t cac oea aa t t off oez t t hi t odd z cdd t column ras asr v address il ih v t rcs t row rah asc t t cas il v ih v ras il v ih v t rcd rad t t wrp t rrh cah t t wrh t t rsh t chr ras t asr t row crp t rc t t rp rc t rp t
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 20 1998-10-01 hidden refresh early write cycle spt03035 "h" or "l" wrp column row address (output) (input) i/o i/o ol v oh v in v v il we il v ih v v il valid data t ds t wcs t dh wp t wch t t asr v cas ih v t il ih v ras v il ih v ras asc rah t t t rad rcd t t cah t rsh t rc t rp t row hi z t wrh rc t ras chr t t asr t crp t rp t
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 21 1998-10-01 cas-before- ras refresh counter test cycle spt03036 "h" or "l" t wch t t dzc t (inputs) i/o (outputs) i/o oh ol v il v v ih v oe we write cycle il il v ih v v ih v i/o (inputs) i/o (outputs) ol v oh v il v ih v t ds z hi data in t wrp wrh t dh t t dzo wcs t t t clz oe we il v ih v il v ih v address cas ih il v v v il ih v read cycle ras v ih il v wrp t wrh t t rcs aa t cac t asc t t cah column csr t chr t cp t ras t rwl cwl t data out t oez t off t odd oea t rrh ral cas t cdd t rch t t asr row rsh t t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 22 1998-10-01 test mode entry spt03042 "h" or "l" ol oh i/o (inputs) (outputs) i/o v v v il oe we v ih v ih v il v il v ih off t oez t cdd t hi z odd t cas address ih v v il v il ras v ih v ih v il rpc t t cp t rp rah wts t row asr t t t wth csr t t chr hi z t rc ras t t rpc crp t t rp
hyb 5(3)117805/bsj-50/-60 2m 8 edo-dram semiconductor group 23 1998-10-01 package outlines plastic package p-soj-28-3 (400mil) (smd) (plastic small outline j-leaded) gpj05699 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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